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low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 1 of 13 approved product fs786/787 features ? spread spectrum clock generator (sscg) with 1x spread and 1x non-spread output. ? 6 to 82 mhz operating frequency range. ? modulates external clocks including crystals, crystal oscillators and ceramic resonators. ? programmable modulation with simple r-c external loop filter (lf) ? provides two output clocks, one modulated and one non-modulated clock. ? center spread modulation. ? 3 - 5 volt power supply. ? ttl/cmos compatible outputs. ? low short term jitter. ? low power dissipation; 3.3 vdc = 37 mw ? typical 5.0 vdc = 115 mw - typical ? available in 8 pin soic package. applications ? desktop/notebook computers ? printers, copiers and mfp ? scanners and fax ? lcd displays and monitors ? cd-rom, vcd and dvd ? automotive and embedded systems ? networking, lan/wan ? digital cameras and camcorders ? modems benefits ? programmable emi reduction ? fast time to market ? lower cost of compliance ? no degradation in rise/fall times ? lower component and pcb layer count product description the cypress fs786/787 are spread spectrum clock generator ics (sscg) designed for the purpose of reducing electro magnetic interference (emi) found in today?s high-speed digital systems. the fs786/787 sscg clocks use an cypress proprietary technology to modulate the input clock frequency, fsout by modulating the frequency of the digital clock. by modulating the reference clock the measured emi at the fundamental and harmonic frequencies of fsout is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements without degrading digital waveforms. the cypress fs786/787 clocks are very simple and versatile devices to use. range selection is performed via one pin, d0. the fs786/787 are designed to operate over a very wide range of input frequencies and provide one modulated and one non-modulated output. the fs786/787 devices have a simple frequency selection table that allows operation from 6 mhz to 82 mhz in two separate ranges and two separate parts. the bandwidth of the frequency spread at fsout is determined by the values of the loop filter components. the modulation rate is determined internally by the input frequency and the selected input frequency range. the bandwidth of these products can be programmed from as little as 0.6% up to as much as 4.0% by selecting the proper loop filter value. refer to the loop filter selection chart on page 6 for recommended values. due to a wide range of application requirements, an external loop filter (lf) is used on the fs786/787 products. the user can select the exact amount of frequency modulation suitable for the application. using a fixed internal loop filter would severely limit the use of a wide range of modulation bandwidths (spread %) to a few discrete values. refer to fs791/2/4 products for applications requiring 80 to 140 mhz frequency range.
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 2 of 13 approved product fs786/787 block diagram figure 1. ordering information product number frequency range package type production flow fs786bz 16 ? 32 mhz, 64 ? 82 mhz 8 pin 150 mil soic commercial, 0 to 70 c fs787bz 6 ? 14 mhz, 34 ? 62 mhz 8 pin 150 mil soic commercial, 0 to 70 c marking example: date code fs786bzb (fs787bzb) lot number fs786bz package z = soic (150 mil) revision device number phase detector vco 1 2 xin xout 10 pf. reference divider 8 pf 8 pf 250 k vco / n modulation control input control logic output divider and mux power contol logic 3 8 5 4 vdd d0 fsout loop filter vss 7 vdd 6 refout
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 3 of 13 approved product fs786/787 pin configuration refer to page 11 for package dimensions. pin description pin no. pin name i/o type description 1/2 xin / xout i/o analog pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal. xin may be connected to ttl/cmos external clock source. if xin connected to external clock other than crystal, leave xout (pin 2) unconnected. 3 d0 i cmos/ttl input frequency range selection. has internal pull-up resistor. fs786 0 = 16 ? 32 mhz, 1 = 64 ? 82 mhz. fs787 0 = 6 ? 14 mhz, 1 = 34 ? 62 mhz. 4 lf i analog loop filter. single ended tri-state output of the phase detector. a passive rc filter is connected to the loop filter pin (lf). 5 vss p power power supply ground. 6 refout o cmos/ttl non-modulated clock output of reference oscillator. 7 fsout o cmos/ttl modulated clock output of reference oscillator. frequency is center spread and 1x of reference clock. 8 vdd p power positive power supply. table 1. pin description output frequency selection product number fsout frequency scaling description fs786 1x 1x modulated clock + 1x non-modulated clock fs787 1x 1x modulated clock + 1x non-modulated clock table 2. fsout sscg (modulated output clock) product selection 1 2 3 4 8 7 6 5 xin xout lf vdd fsout vss fs786/787 d0 refout
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 4 of 13 approved product fs786/787 this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range, vss < ( vin or vout) < vdd. all digital inputs are tied high or low internally. refers to electrical specifications for operating supply range. absolute maximum ratings 1 item symbol min max units operating voltage vdd 3.0 6.0 vdc input, relative to vss virvss -0.3 vdd +0.3 vdc output, relative to vss vorvss -0.3 vdd +0.3 vdc avdd relative to dvdd ? vpp -100 +100 mv avss relative to dvss ? vss -100 +100 mv temperature, operating top 0 + 70 0 c temperature, storage tst - 65 + 150 0 c table 3 electrical characteristics characteristic symbol min typ max units input low voltage vil - - 0.3 * vdd vdc input high voltage vih 0.7 * vdd - - vdc input low current iil - - 100 a input high current iih - - 100 a output low voltage iol= 10ma, vdd = 5v vol - - 0.4 vdc output high voltage ioh = 10ma, vdd = 5v voh vdd-1.0 - - vdc output low voltage iol= 6ma, vdd = 3.3v vol - - 0.4 vdc output high voltage ioh = 5ma,vdd = 3.3v voh 2.4 - - vdc resistor, pull up (pin-3) rpu 60k 125k 200k ohms input capacitance (pin-1) c in1 -8 - pf output capacitance (pin-2) c in2 -8 - pf 5 volt dynamic supply current (c l = no load) icc - 38 - ma 3.3 volt dynamic supply current (c l = no load) icc - 20 - ma short circuit current (fsout) isc - 25 - ma test measurements performed at vdd = 3.3v and 5.0v 10%, xin = 48 mhz, ta = 0 c to 70 c table 4 1 single power supply: the voltage on any input or i/o pin cannot exceed the power pin during power-up.
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 5 of 13 approved product fs786/787 timing characteristics characteristic symbol min. typ. max. units fsout rise time @ 10 - 90% at 5 vdc ttlh 2.0 2.2 2.5 ns fsout fall time @ 10 - 90% at 5 vdc tthl 1.7 2.0 2.2 ns fsout rise time @ 0.8 - 2.0v at 5 vdc ttlh 0.50 0.65 0.75 ns fsout fall time @ 0.8 - 2.0v at 5 vdc tthl 0.50 0.65 0.75 ns fsout rise time @ 10 - 90% at 3.3 vdc ttlh 2.6 2.65 2.9 ns fsout fall time @ 10 - 90% at 3.3 vdc tthl 2.0 2.1 2.2 ns fsout rise time @ 0.8 - 2.0v at 3.3 vdc ttlh 0.8 0.95 1.1 ns fsout fall time @ 0.8 - 2.0v at 3.3 vdc tthl 0.78 0.85 0.9 ns fsout duty cycle @ 50% of vdd tsymf1 45 50 55 % fsout, cycle to cycle jitter, 48 mhz @ 3.30 vdc ccj - 320 370 ps fsout, cycle to cycle jitter, 48 mhz @ 5.00 vdc ccj - 310 360 ps fsout, cycle to cycle jitter, 72 mhz @ 3.30 vdc ccj - 270 325 ps fsout, cycle to cycle jitter, 72 mhz @ 5.00 vdc ccj - 390 440 ps refout rise time @ 10 ? 90% at 5 vdc ttlh 4.2 4.5 4.9 ns refout fall time @ 10 ? 90% at 5 vdc tthl 2.5 2.65 2.8 ns refout rise time @ 0.8 ? 2.0 v at 5 vdc ttlh 0.74 0.80 0.86 ns refout fall time @ 0.8 ? 2.0 v at 5 vdc tthl 0.76 0.85 0.93 ns refout rise time @ 10 ? 90% at 3.3 vdc ttlh 4.6 4.95 5.3 ns refout fall time @ 10 ? 90% at 3.3 vdc tthl 2.5 2.65 2.8 ns refout rise time @ 0.8 ? 2.0 v at 3.3 vdc ttlh 1.4 1.5 1.6 ns refout fall time @ 0.8 ? 2.0 v at 3.3 vdc tthl 1.00 1.1 1.2 ns unless otherwise indicated, measurements performed at vdd = 3.3 and 5.0v 10%, ta = 0 c to 70 c, cl = 15pf, xin = 48 mhz. table 5 application selection table select the row containing the frequency for the intended application. read the device number and d0 programming in cells to the right of fin. the modulation rate is also given below. fin (mhz) (pin 1/2) d0 (pin 3) modulation rate device to use 6 ? 14 0 fin/120 fs787bzb 16 ? 32 0 fin/240 fs786bzb 34 - 62 1 fin/480 fs787bzb 64 - 82 1 fin/720 fs786bzb table 6
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 6 of 13 approved product fs786/787 fs786 loop filter selection chart the following table provides a list of recommended loop filter values for the fs786. the fs786 is divided into 2 ranges and operates at both 3.3 and 5.0 vdc. the loop filter at the right is representative of the loop filter components in the table below. fs786 recommended loop filter values. c7 (pf.) @ +3.3 vdc +/- 5% (r6 = 3.3k) input (mhz) d0 (pin 3) bw = 1.0% (note 2) bw = 1.5% (note 2) bw = 2.0% (note 2) bw = 2.5% (note 2) bw = 3.0% (note 2) bw = 3.5% (note 2) bw = 4.0% (note 2) 16 0 10000 980 760 580 470 410 385 18 0 1200 750 580 470 415 370 300 20 0 1000 730 470 390 320 220 190 22 0 960 640 410 270 230 200 180 24 0 920 400 250 210 180 160 150 26 0 660 300 220 180 150 140 120 28 0 470 230 180 150 130 100 70 30 0 470 180 140 120 100 80 60 32 0 330 170 120 100 82 68 47 64 1 1180 860 560 410 340 290 230 65 1 1180 850 540 400 330 280 220 66 1 1180 760 560 350 260 220 210 68 1 1180 750 500 320 260 230 210 70 1 1120 740 470 370 300 240 170 72 1 1160 780 470 300 250 220 190 74 1 1110 770 470 280 230 210 190 76 1 1000 720 440 240 210 190 170 78 1 910 670 270 210 190 170 160 80 1 900 620 260 210 190 170 156 82 1 900 540 250 210 190 170 150 c7 (pf.) @ +5.0 vdc +/- 5% (r6 = 3.3k) input (mhz) d0 bw = 1.0% (note 2) bw = 1.5% (note 2) bw = 2.0% (note 2) bw = 2.5% (note 2) bw = 3.0% (note 2) bw = 3.5% (note 2) bw = 4.0% (note 2) 16 0 2200 860 640 520 420 375 330 18 0 2200 770 575 450 375 325 275 20 0 1200 600 425 325 250 170 220 22 0 870 490 290 230 200 180 170 24 0 720 320 220 180 160 140 130 26 0 465 235 185 150 130 100 75 28 0 380 205 160 130 100 90 80 30 0 220 178 135 95 85 80 72 62 1 note 4. 800 580 430 330 250 180 64 1 note 4. 720 490 375 285 200 140 66 1 note 4. 630 400 320 240 150 100 68 1 note 4. 690 365 285 225 170 140 70 1 note 4. 650 330 250 210 190 180 72 1 note 4. 575 340 250 210 190 170 74 1 note 4. 500 355 245 205 180 165 76 1 note 4. 550 330 230 200 175 160 78 1 note 4. 600 290 220 190 170 155 80 1 note 4. 570 240 210 185 165 150 82 1 note 4. 540 250 200 180 160 140 notes: 1. if the value selected from the above chart is not a standard value, use the next available larger value. 2. all bandwidths indicated are total peak-to-peak spread. 1% = +0.5% to ? 0.5%. 4% = +2.0% to ? 2.0%. 3. if c8 is not listed in the chart for a particular bw and freq., it is not used in the loop filter. 4. contact factory for these loop filter values and bandwidths less than 1.0%. table 7. c8 r6 c lf (pin 4)
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 7 of 13 approved product fs786/787 fs787 loop filter selection chart the following table provides a list of recommended loop filter values for the fs787. the fs787 is divided into 2 ranges and operates at both 3.3 and 5.0 vdc. refer to the loop filter schematic on previous page for component references. fs787 recommended loop filter values. c7 (pf.) @ +3.3 vdc +/- 5% (r6 = 3.3k) input (mhz) d0 bw = 1.0% (note 2) bw = 1.5% (note 2) bw = 2.0% (note 2) bw = 2.5% (note 2) bw = 3.0% (note 2) bw = 3.5% (note 2) bw = 4.0% (note 2) 6 0 10,000/1000 1500 880 750 680 620 540 8 0 10,000/330 960 790 620 500 430 390 10 0 1000 660 440 350 290 230 200 12 0 800 410 290 215 195 180 160 14 0 560 220 190 150 130 100 75 34 1 10000 860 640 520 430 380 330 36 1 2200 820 620 470 400 330 290 38 1 1500 690 520 410 340 290 240 40 1 960 600 420 340 280 220 160 42 1 940 620 380 275 230 210 180 44 1 950 680 400 250 210 190 170 46 1 900 580 270 220 190 180 165 48 1 790 440 260 210 180 160 140 50 1 660 360 250 190 170 150 140 52 1 470 325 220 185 155 135 120 54 1 470 270 200 170 140 130 100 56 1 445 250 185 150 120 85 47 58 1 430 210 165 130 100 65 33 60 1 295 185 150 120 100 90 82 62 1 270 220 150 120 100 82 68 c7 (pf.) @ +5.0 vdc +/- 5% (r6 = 3.3k) input (mhz) d0 bw = 1.0% (note 2) bw = 1.5% (note 2) bw = 2.0% (note 2) bw = 2.5% (note 2) bw = 3.0% (note 2) bw = 3.5% (note 2) bw = 4.0% (note 2) 6 0 1110 1000 900 800 690 590 490 8 0 1130 940 720 550 450 390 270 10 0 1000 640 420 340 270 200 130 12 0 740 330 220 190 170 150 130 14 0 440 230 170 135 100 70 47 32 1 note 4. 900 670 510 420 370 330 34 1 note 4. 890 635 470 380 325 270 36 1 note 4. 870 600 430 340 280 210 38 1 note 4. 795 500 345 276 242 202 40 1 note 4. 720 410 260 212 204 194 42 1 930 610 320 230 196 184 172 44 1 710 500 230 200 180 170 150 46 1 1000 375 255 185 165 150 130 48 1 1000 250 180 170 150 130 110 50 1 750 300 180 160 140 120 100 52 1 500 310 185 155 130 110 85 54 1 460 250 165 130 100 97 82 56 1 420 190 145 110 90 85 80 58 1 405 200 225 95 80 75 70 60 1 385 220 110 80 75 70 60 notes: 1. if the value selected from the above chart is not a standard value, use the next available larger value. 2. all bandwidths indicated are total peak-to-peak spread. 1% = +0.5% to ? 0.5%. 4% = +2.0% to ? 2.0%. 3. if c8 is not listed in the chart for a particular bw and freq., it is not used in the loop filter. 4. contact factory for these loop filter values and bandwidths less than 1.0%. table 8.
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 8 of 13 approved product fs786/787 sscg modulation profile the digital control input d0 determines the modulation frequency of the fs786 and fs787 products. the modulation frequency is determined by dividing the input frequency by a constant divisor. one of 4 divisor numbers are used, depending on the device and setting of d0. the modulation frequency of the fs786/787 can be determined from table 8. select the device and input frequency on table 8 and read the modulation divider. then, divide the input frequency by the modulation divider. device d0 input frequency range (mhz) modulation divider number fs787 0 6 to 14 120 fs786 0 16 to 32 240 fs787 1 32 to 62 480 fs786 1 64 to 82 720 table 11 figure 5. frequency profile in time domain with the correct loop filter connected to pin 4, the profile in figure 5 above will provide the best emi reduction. this profile can be seen on a time domain analyzer. xin + .5% - .5% time (microseconds) 1.0% total
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 9 of 13 approved product fs786/787 fc = 20 mhz fmin = 19.8 mhz fmax = 20.2 mhz theory of operation the fs786/787 devices are phase lock loop (pll) type clock generators using direct digital synthesis (dds). by precisely controlling the bandwidth of the output clock, the fs786/787 products become a low emi clock generator. the theory and detailed operation of these products will be discussed in the following sections. emi all clocks generate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50 %. because of the 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e.; 3 rd , 5 th , 7 th etc. it is possible to reduce the amount of energy contained in the fundamental and harmonics by increasing the bandwidth of the fundamental clock frequency. conventional digital clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for electro-magnetic interference (emi). conventional methods of reducing emi have been to use shielding, filtering, multi-layer pcb ? s etc. the fs786 and 787 use the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the q of the clock. sscg the fs786/787 products use a unique method of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak to peak and cycle to cycle. the fs78x products take a narrow band digital reference clock in the range 6 - 82 mhz and produce a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to an sscg clock, consider that we have a 20 mhz clock with a 50 % duty cycle. from a 20 mhz clock we know the following; clock frequency = fc = 20 mhz. clock period = tc = 1/20 mhz=50 ns consider that this 20 mhz clock is applied to the xin input of the fs78x, either as an externally driven clock or as the result of a parallel resonant crystal connected to pins 1 and 2 of the fs78x. also consider that the products are operating from a 5-volt dc power supply and the loop filter is set for a total bandwidth spread of 2%. refer to table 6 on page 6. from the above parameters, the output clock at fsout will be sweeping symmetrically around a center frequency of 20 mhz. the minimum and maximum extremes of this clock will be +200 khz and - 200 khz. so, we have a clock that is sweeping from 19.8 mhz to 20.2 mhz and back again. if we were to look at this clock on a spectrum analyzer we would see the picture in figure 7. keep in mind that this is a drawing of a perfect clock with no noise. figure 7. 50% 50% tc = 50 ns. 20 mhz unmodulated clock
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 10 of 13 approved product fs786/787 tc = 50.50 tc =49.50 ns. we see that the original 20 mhz reference clock is at the center frequency, cf, and the minimum and maximum extremes are positioned symmetrically about the center frequency. this type of modulation is called center-spread . figure 8 shows a 20 mhz clock, as it would be seen on an oscilloscope. the top trace is the non-modulated reference clock,. the bottom trace is the modulated clock at pin 6. from this comparison chart you can see that the frequency is decreasing and the period of each successive clock is increasing. the tc measurements on the left and right of the bottom trace indicate the max. and min. extremes of the clock. intermediate clock changes are small and accumulate to achieve the total period deviation. the reverse of this figure would show the clock going from min. extreme back to the high extreme. figure 8. period comparison chart looking at figure 7, you will note that the peak amplitude of the 20 mhz non-modulated clock is higher than the wideband modulated clock. this difference in peak amplitudes between modulated and unmodulated clocks is the reason why sscg clocks are so effective in digital systems. this figure refers to the fundamental frequency of a clock. a very important characteristic of the sscg clock is that the bandwidth of the fundamental frequency is multiplied by the harmonic number. in other words, if the bandwidth of a 20 mhz clock is 200 khz, the bandwidth of the 3 rd harmonic will be 3 times 200, or 600 khz. the amount of bandwidth is relative to the amount of energy in the clock. consequently, the wider the bandwidth, the greater the energy reduction of the clock. most applications will not have a problem meeting agency specifications at the fundamental frequency. it is the higher harmonics that usually cause the most problems. with an sscg clock, the bandwidth and peak energy reduction increases with the harmonic number. consider that the 11 th harmonic of a 20 mhz clock is 220 mhz. with a total spread of 200 khz at 20 mhz, the spread at the 11 th harmonic would be 2.20 mhz which greatly reduces the peak energy content. it is typical to see as much as 12 to 18 db. reduction at the higher harmonics, due to a modulated clock. the difference in the peak energy of the modulated clock and the non-modulated clock in typical applications will see a 2 - 3 db. reduction at the fundamental and as much as 8 - 10 db. reduction at the intermediate harmonics, 3 rd , 5 th , 7 th etc. at the higher harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodulated clock, by as much as 12 to 18 db.
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 11 of 13 approved product fs786/787 application notes and schematic the schematic at the right is configured for the following parameters; package selected = fs786 by selecting the fs786 or the fs787 and selecting d0 low or high, any input frequency from 6 to 82 mhz can be modulated. in addition to providing a modulated low emi clock, the fs786 and fs787 also provide a non- modulated clock which is a buffered copy of the reference oscillator. package drawing and dimensions vdd ** ** occasionally, c8 is used to create a second pole f or this loop f ilter. ref er to loop filter selection table. mount loop filter components as close to lf pin as possible. . crystal is a 20 mhz, fundamental, with 18 pf load capacitance. if crystal load capacitance is different than 18 pf, c1 and c2 must be re-calculated. for third overtone crystals, a parallel or series resonant trap is required. bandwidth is determined by the value of the loop filter components connected to pin 4. r6 c2 0.1 uf c4 27 pf c5 27 pf y1 20 m hz c8 c7 fs786 xi n 1 xout 2 d0 3 lf 4 vss 5 refout 6 fsout 7 vdd 8 vdd refout fsout
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 12 of 13 approved product fs786/787 l c h a d be a1 a2 a e h imi xxyy fs786bzb lot # pin 1 8 pin soic outline dimensions inches millimeters symbol min nom max min nom max a 0.061 0.064 0.068 1.55 1.63 1.73 a 1 0.004 0.006 0.0098 0.127 0.150 0.250 a 2 0.055 0.058 0.061 1.40 1.47 1.55 b 0.0138 0.016 0.0192 0.35 0.41 0.49 c 0.0075 0.008 0.0098 0.19 0.20 0.25 d 0.189 0.194 0.196 4.80 4.93 4.98 e 0.150 0.155 0.157 3.81 3.94 3.99 e 0.050 bsc 1.270 bsc h .230 .236 .244 5.84 5.99 6.20 h 0.010 0.013 0.016 0.25 0.33 0.41 a 0 5 8 0 5 8 l 0.016 0.025 0.035 0.41 0.64 0.89 cypress semiconductor corporation disclaimer cypress semiconductor corporation reserves the right to change or modify the information contained in this data sheet, without notice. cypress semiconductor corporation does not assume any liability arising out of the application or use of any product or circuit described herein cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others. cypress semiconductor corporation does not authorize its products for use as critical components in life-support systems or critical m edical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user.
low emi spread spectrum clock cypress semiconductor corporation document#: 38-07031 rev. *a 12/14/02 http://www.cypress page 13 of 13 approved product fs786/787 document title: fs786/787 low emi spread spectrum clock document number: 38-07031 rev. ecn no. issue date orig. of change description of change ** 106959 06/11/01 ika convert from imi to cypress *a 122680 12/14/02 rbi added power up requirements to absolute maximum ratings information.

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